<div dir="ltr">the "waitfordma" routine from our notes should work for that. Only thing to be careful of is that you wait for the right TCC code. Of course, the side effect of having that wrong would be waiting forever<br>
<br>Good luck,<br>Doug<br> <br><br><div class="gmail_quote">On Thu, Oct 16, 2008 at 7:18 PM, Ryan Merton <span dir="ltr"><<a href="mailto:lucidsmog@gmail.com">lucidsmog@gmail.com</a>></span> wrote:<br><blockquote class="gmail_quote" style="border-left: 1px solid rgb(204, 204, 204); margin: 0pt 0pt 0pt 0.8ex; padding-left: 1ex;">
Hi Doug,<br>
<br>
Your guess was correct in that waitfordma was in fact not waiting for<br>
anything. Throwing in an arbitrary spin loop allowed for everything<br>
to work. Then I had it print how many times it sat in it's<br>
theoretical "wait for DMA to finish" loop, and the number is always<br>
zero.<br>
<br>
I guess that's what I get for using someone else's code, even if it<br>
was from an example TI provided!<br>
<br>
I haven't worked out yet how to correctly wait for it, but I'm sure it<br>
can't be that hard!<br>
<br>
Thanks,<br>
<font color="#888888">Ryan<br>
</font><div><div></div><div class="Wj3C7c"><br>
On Thu, Oct 16, 2008 at 3:36 PM, Wenstrand, Doug S.<br>
<<a href="mailto:Douglas.Wenstrand@jhuapl.edu">Douglas.Wenstrand@jhuapl.edu</a>> wrote:<br>
><br>
> Yes, there are some things that we need to do to setup SDRAM, and they<br>
> are in the GEL file, so check to make sure that you are using the gel<br>
> file for the c6713dsk. CCS sets these registers when you connect the<br>
> emulator, that why we don't in our software.<br>
><br>
> The reason I don't see that being an issue is that I thought we saw<br>
> beautiful data that you had extracted from SDRAM and put into L2. Are<br>
> you sure that you are waiting for the DMA transfers to happen correctly?<br>
> If you can step through all cases, and see the right FFT show up in the<br>
> right place in external memory, and only when free-running it goes bad,<br>
> I suspect that the waiting process might not be correct.<br>
><br>
> Two things :<br>
><br>
> 1) see how long you actually wait in waitfordma. If it seems too fast,<br>
> something is wrong.<br>
> 2) send me the project at the website... Lab6_merton_test.zip or<br>
> something like that. I'll take a look as well<br>
><br>
> Seeya<br>
> Doug<br>
><br>
><br>
><br>
><br>
><br>
> ---------------------------------------<br>
> D. S. Wenstrand<br>
> Johns Hopkins University<br>
> Applied Physics Laboratory<br>
> (240) 228-4282<br>
><br>
><br>
> -----Original Message-----<br>
> From: <a href="mailto:dspforum-bounces@echelonembedded.com">dspforum-bounces@echelonembedded.com</a><br>
> [mailto:<a href="mailto:dspforum-bounces@echelonembedded.com">dspforum-bounces@echelonembedded.com</a>] On Behalf Of Ryan Merton<br>
> Sent: Thursday, October 16, 2008 3:01 PM<br>
> To: <a href="mailto:dspforum@echelonembedded.com">dspforum@echelonembedded.com</a><br>
> Subject: [Dspforum] More troubles with lab 6<br>
><br>
> Doug,<br>
><br>
> Remember how we figured out that my problem last night was related to<br>
> the bit reversal indexing? It wasn't. I went home, and I did in fact<br>
> call the routine with the correct parameters to begin with.<br>
> Breakpointing around the FFT and saving data along the way leads me to<br>
> see no problem at all. Only after I remove the breakpoints and let it<br>
> go freerunning do things start to mess up.<br>
><br>
> Is there some magic we have to configure to get the SDRAM timings right,<br>
> or DMA configuration registers aside from the QDMA registers?<br>
><br>
> I breakpointed after bringing the time domain data in from ext ram,<br>
> after the FFT and bit reversal, and after the FFT data is stored off to<br>
> RAM. At each of those steps for the first 7 FFTs I saved the contents<br>
> of external RAM. It all looks fine. I got tired of it, removed the<br>
> breakpoints, and let it run, then dumped it all at the end... and<br>
> starting at about the 13th FFT the FFT data is not right.<br>
> The time domain data remains intact. If I do the first 3 FFTs and let<br>
> it go free running, it messes up around the 6th or 7th FFT.<br>
><br>
> Any ideas? I am using this to wait for the DMA to finish: while<br>
> (!(EDMA_getPriQStatus() & EDMA_OPT_PRI_HIGH)); I stole that line right<br>
> from the CSL user's guide. I am tempted to put something like<br>
> for(x=0;x<10000000;x++){blah=sin(x);} and see if it works then.<br>
><br>
> Thanks,<br>
> Ryan<br>
><br>
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